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M41T81
SERIAL ACCESS RTC WITH ALARMS
FEATURES SUMMARY s 2.0 TO 5.5V CLOCK OPERATING VOLTAGE
s
Figure 1. 8-pin SOIC Package
8 1
COUNTERS FOR TENTHS/HUNDREDTHS OF SECONDS, SECONDS, MINUTES, HOURS, DAY, DATE, MONTH, YEAR, and CENTURY AUTOMATIC SWITCH-OVER and DESELECT CIRCUITRY SERIAL INTERFACE SUPPORTS I2C BUS (400KHz PROTOCOL) PROGRAMMABLE ALARM and INTERRUPT FUNCTION (valid even during Battery Back-up Mode) WATCHDOG TIMER LOW OPERATING CURRENT OF 400A BATTERY BACK-UP NOT RECOMMENDED FOR 3.0V APPLICATIONS (CAPACITOR BACK-UP ONLY) BATTERY OR SUPER-CAP BACK-UP OPERATING TEMPERATURE OF -40 TO 85C ULTRA-LOW BATTERY SUPPLY CURRENT OF 1A PACKAGE OPTIONS INCLUDE A 28-LEAD or 18-LEAD EMBEDDED CRYSTAL SOIC
s
SO8 (M)
s
Figure 2. 28-pin (300mil) SOIC Package*
EMBEDDED Crystal
s
s s s
SOX28 (MX)
s s
Figure 3. 18-pin (300mil) SOIC Package*
EMBEDDED Crystal
s
18
s
1
SOX18 (MY)
September 2003
Rev. 2.0
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M41T81
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 5. 8-pin SOIC (M) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 7. 28-pin, 300mil SOIC (MX) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 6. 18-pin, 300mil SOIC (MY) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 8. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 10. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 11. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 12. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 13. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 14. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 15. Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 16. WRITE Mode Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 17. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 9. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 . . . . 14 . . . . 14 . . . . 14
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TIMEKEEPER(R) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 10. TIMEKEEPER(R) Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 18. Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Figure 19. Back-up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 12. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Preferred Initial Power-on Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 13. Preferred Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 20. Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 21. Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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M41T81
SUMMARY DESCRIPTION The M41T81 Serial Access TIMEKEEPER(R) SRAM is a low power Serial RTC with a built-in 32.768 KHz oscillator (external crystal controlled). Eight bytes of the SRAM (see Table 10, page 16) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 12 bytes of SRAM provide status/ control of Alarm, Watchdog and Square Wave functions. Addresses and data are transferred serially via a two line, bi-directional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T81 has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the SRAM and clock operations can be supplied by a
small lithium button supply when a power failure occurs. Functions available to the user include a non-volatile, time-of-day clock/calendar, Alarm interrupts, Watchdog Timer and programmable Square Wave output. The eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. The M41T81 is supplied in either an 8-pin SOIC or an 18-pin (MY) or 28-pin (MX), 300mil SOIC package which includes an embedded 32kHz crystal. The 8-pin and 28-pin, embedded crystal SOIC requires only a user-supplied battery to provide nonvolatile operation.
Figure 4. Logic Diagram
VCC VBAT
Table 1. Signal Names
XI(1) XO(1) Oscillator Input Oscillator Output Interrupt / Output Driver / Frequency Test / Square Wave (Open Drain) Serial Data Input/Output Serial Clock Input Battery Supply Voltage Supply Voltage Ground
XI(1) XO(1) SCL SDA M41T81 IRQ/FT/OUT/SQW
IRQ/OUT/ FT/SQW SDA SCL VBAT VCC VSS
VSS
AI04613
Note: 1. For SO8 package only.
Note: 1. For SO8 package only.
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M41T81
Figure 5. 8-pin SOIC (M) Connections
XI XO VBAT VSS 1 2 3 4 8 7 6 5 VCC IRQ/FT/OUT/SQW SCL SDA
AI04769
Figure 7. 28-pin, 300mil SOIC (MX) Connections
M41T81
Figure 6. 18-pin, 300mil SOIC (MY) Connections
NC NC NC NC NC NC NC VBAT VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 M41T81 12 11 10 NC NC NC VCC NC IRQ/FT/OUT/SQW NC SCL SDA
AI07830
NC NC NC NC NC NC NC NC NC NC NC NC VBAT VSS
1 28 27 2 26 3 25 4 24 5 23 6 7 M41T81 22 21 8 20 9 19 10 18 11 17 12 16 13 15 14
VCC NC IRQ/FT/OUT/SQW NC VSS NC SCL NC VCC(1) NC IRQ/FT/OUT/SQW(1) SDA SCL(1) SDA(1)
AI07805
Note: 1. No Connect (NC) pin for 28-pin SOIC, but should be considered to have indicated function in anticipation of replacement with 18-pin SOIC.
Figure 8. Block Diagram
REAL TIME CLOCK CALENDAR 32KHz OSCILLATOR
CRYSTAL
RTC W/ALARM & CALIBRATION
AFE
SDA
WATCHDOG I2C INTERFACE
WDF
IRQ/FT/OUT/SQW(1)
SCL WRITE PROTECT
SQUARE WAVE
SQWE
VCC
INTERNAL POWER
VBAT VSO(2) COMPARE
Note 1. Open drain output Note 2. VSO = VBAT - 0.5V (typ)
AI04616
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M41T81
MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 2. Absolute Maximum Ratings
Sym TSTG VCC TSLD(1) VIO IO PD Parameter Storage Temperature (VCC Off, Oscillator Off) Supply Voltage Lead Solder Temperature for 10 Seconds Input or Output Voltages Output Current Power Dissipation SOIC Value -55 to 125 -0.3 to 7 260 -0.3 to Vcc+0.3 20 1 Unit C V C V mA W
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Reflow at peak temperature of 215C to 225C for < 60 seconds (total thermal budget not to exceed 180C for between 90 to 120 seconds).
CAUTION: Negative undershoots below -0.3 volts are not allowed on any pin while in the Battery Back-Up Mode
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M41T81
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
M41T81 2.0 to 5.5V -40 to 85C 100pF 50ns 0.2VCC to 0.8 VCC 0.3VCC to 0.7 VCC
Figure 9. AC Measurement I/O Waveform
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 4. Capacitance
Symbol CIN COUT(3) tLP Input Capacitance Output Capacitance Low-pass filter input time constant (SDA and SCL) Parameter(1,2) Min Max 7 10 50 Unit pF pF ns
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
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M41T81
Table 5. DC Characteristics
Sym ILI ILO ICC1 ICC2 VIL VIH VOL VBAT(2) IBAT
Note: 1. 2. 3. 4. 5.
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (standby) Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage (Open Drain)(5) Battery Supply Voltage Battery Supply Current
Test Condition(1) 0V VIN VCC 0V VOUT VCC Switch Freq = 400kHz SCL,SDA = VCC - 0.3V
Min
Typ
Max 1 1 400 100
Unit A A A A V V V V V A
-0.3 0.7VCC IOL = 3.0mA IOL = 10mA 2.5(3) TA = 25C, VCC = 0V Oscillator ON, VBAT = 3V 3 0.6
0.3VCC VCC + 0.3 0.4 0.4 3.5(4) 1
Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.0 to 5.5V (except where noted). STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply. After switchover (VSO), VBAT (min) can be 2.0V for crystal with RS = 40K. For rechargeable back-up, VBAT (max) may be considered VCC. For IRQ/FT/OUT/SQW pin (Open Drain)
Table 6. Crystal Electrical Characteristics
Sym fO RS CL Parameter(1,2,3) Resonant Frequency Series Resistance Load Capacitance 12.5 Min Typ 32.768 60 Max Units kHz k pF
Note: 1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 2. Load capacitors are integrated within the M41T81. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
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M41T81
OPERATION The M41T81 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 20 bytes contained in the device can then be accessed sequentially in the following order: 1. Tenths/Hundredths of a Second Register 2. Seconds Register 3. Minutes Register 4. Century/Hours Register 5. Day Register 6. Date Register 7. Month Register 8. Year Register 9. Control Register 10. Watchdog Register 11 - 16. Alarm Registers 17 - 19. Reserved 20. Square Wave Register The M41T81 clock continually monitors VCC for an out-of-tolerance condition. Should VCC fall below VSO, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. The device also automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. For more information on Battery Storage Life refer to Application Note AN1012. 2-Wire Bus Characteristics The bus is intended for communication between different ICs. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is High.
- Changes in the data line, while the clock line is High, will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy. Both data and clock lines remain High. Start data transfer. A change in the state of the data line, from high to Low, while the clock is High, defines the START condition. Stop data transfer. A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition. Data Valid. The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves." Acknowledge. Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition.
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M41T81
Figure 10. Serial Bus Data Transfer Sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
Figure 11. Acknowledgement Sequence
START SCL FROM MASTER 1 2 8 CLOCK PULSE FOR ACKNOWLEDGEMENT 9
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
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M41T81
Figure 12. Bus Timing Requirements Sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
Table 7. AC Characteristics
Sym fSCL tLOW tHIGH tR tF tHD:STA tSU:STA tSU:DAT(2) tHD:DAT tSU:STO tBUF Parameter(1) SCL Clock Frequency Clock Low Period Clock High Period SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time (after this period the first clock pulse is generated) START Condition Setup Time (only relevant for a repeated start condition) Data Setup Time Data Hold Time STOP Condition Setup Time Time the bus must be free before a new transmission can start 600 600 100 0 600 1.3 Min 0 1.3 600 300 300 Typ Max 400 Units kHz s ns ns ns ns ns ns s ns s
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.0 to 5.5V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
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M41T81
READ Mode In this mode the master reads the M41T81 slave after setting the slave address (see Figure 14, page 12). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge Bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ Mode Control Bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge Clock. The M41T81 slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to "An+2." Figure 13. Slave Address Location
R/W
This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume due to a Stop Condition or when the pointer increments to any non-clock address (08h-13h). Note: This is true both in READ Mode and WRITE Mode. An alternate READ Mode may also be implemented whereby the master reads the M41T81 slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 15, page 13).
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
Figure 14. READ Mode Sequence
START START R/W BUS ACTIVITY: MASTER R/W
SDA LINE
S
WORD ADDRESS (An) ACK
S
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS STOP
DATA n+X
P
AI00899
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NO ACK
ACK
M41T81
Figure 15. Alternative READ Mode Sequence
START STOP DATA n ACK ACK DATA n+1 ACK ACK DATA n+X P NO ACK
AI00895
BUS ACTIVITY: MASTER SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
WRITE Mode In this mode the master transmitter transmits to the M41T81 slave receiver. Bus protocol is shown in Figure 16, page 13. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address "An" will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next Figure 16. WRITE Mode Sequence
START BUS ACTIVITY: MASTER R/W
R/W
and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. The M41T81 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see Figure 13, page 12 and again after it has received the word address and each data byte.
SDA LINE
S
WORD ADDRESS (An) ACK ACK
DATA n
DATA n+1
DATA n+X
P
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00591
ACK
STOP
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M41T81
Data Retention Mode With valid VCC applied, the M41T81 can be accessed as described above with READ or WRITE Cycles. Should the supply voltage decay, the power input will be switched from the VCC pin to the battery when VCC falls below the Battery Back-up Switchover Voltage (VSO). At this time the clock registers will be maintained by the attached battery supply. As VCC continues to fall, the M41T81 Figure 17. Power Down/Up Mode AC Waveforms
VCC VSO tPD SDA SCL DON'T CARE
AI00596
will pass through the Register Bit Reset Voltage (VRST) threshold, not only write protecting itself, but also resetting certain Control Bits (see Table 13, page 21). On power-up, when VCC returns to a nominal value, write protection continues for tREC. For a further, more detailed review of lifetime calculations, please see Application Note AN1012.
tREC
Table 8. Power Down/Up AC Characteristics
Symbol tPD tREC Parameter(1,2) SCL and SDA at VIH before Power Down SCL and SDA at VIH after Power Up Min 0 10 Typ Max Unit nS S
Note: 1. VCC fall time should not exceed 5mV/s. 2. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.0 to 5.5V (except where noted).
Table 9. Power Down/Up Trip Points DC Characteristics
Sym VSO VRST Parameter(1,2) Battery Back-up Switchover Voltage Register Bit Reset Voltage Min VBAT - 0.80 1.1 Typ VBAT - 0.50 Max VBAT - 0.30 2.0 Unit V V
Note: 1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.0 to 5.5V (except where noted).
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M41T81
CLOCK OPERATION The 20-byte Register Map (see Table 10, page 16) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained within the first four registers. Note: A WRITE to any clock register will result in the Tenths/Hundredths of Seconds being reset to "00," and Tenths/Hundredths of Seconds cannot be written to any value other than "00." Bits D6 and D7 of Clock Register 03h (Century/ Hours Register) contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 04h contain the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month and Years. The ninth clock register is the Control Register (this is described in the Clock Calibration section). Bit D7 of Register 01h contains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second. The eight Clock Registers may be read one byte at a time, or in a sequential block. The Control Register (Address location 08h) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the
eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ. Note: When a power failure occurs, the HT Bit will automatically be set to a '1.' This will prevent the clock from updating the TIMEKEEPER(R) registers, and will allow the user to read the exact time of the power-down event. Resetting the HT Bit to a '0' will allow the clock to update the TIMEKEEPER registers with the current time. TIMEKEEPER (R) Registers The M41T81 offers 20 internal registers which contain Clock, Alarm, Watchdog, Flag, Square Wave and Control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer increments to any non-clock address (08h-13h). TIMEKEEPER and Alarm Registers store data in BCD. Control, Watchdog and Square Wave Registers store data in Binary Format.
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M41T81
Table 10. TIMEKEEPER(R) Register Map
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h OUT 0 AFE RPT4 RPT3 RPT2 RPT1 WDF 0 0 0 RS3 AF 0 0 0 RS2 ST 0 CEB 0 0 0 CB 0 0 0 10 Years FT BMB4 SQWE RPT5 HT S BMB3 ABE BMB2 Al 10M BMB1 0 0 10 Date 10M D6 D5 D4 D3 D2 D1 D0 Function/Range BCD Format Seconds Seconds Minutes Century/ Hours Day Date Month Year Control RB1 RB0 Watchdog Al Month Al Date Al Hour Al Min Al Sec 0 0 0 0 0 Flags Reserved Reserved Reserved SQW 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 0-1/00-23 01-7 01-31 01-12 00-99
0.1 Seconds 10 Seconds 10 Minutes 10 Hours 0 0
0.01 Seconds Seconds Minutes Hours (24 Hour Format) Day of Week Date: Day of Month Month Year Calibration BMB0
Alarm Month Alarm Date Alarm Hour Alarm Minutes Alarm Seconds
AI 10 Date AI 10 Hour
Alarm 10 Minutes Alarm 10 Seconds 0 0 0 0 RS1 0 0 0 0 RS0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
Keys: S = Sign Bit FT = Frequency Test Bit ST = Stop Bit 0 = Must be set to '0' BMB0-BMB4 = Watchdog Multiplier Bits CEB = Century Enable Bit CB = Century Bit OUT = Output level ABE = Alarm in Battery Back-up Mode Enable Bit
AFE = Alarm Flag Enable Flag RB0-RB1 = Watchdog Resolution Bits RPT1-RPT5 = Alarm Repeat Mode Bits WDF = Watchdog Flag (Read only) AF = Alarm Flag (Read only) SQWE = Square Wave Enable RS0-RS3 = SQW Frequency HT = Halt Update Bit
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M41T81
Calibrating the Clock The M41T81 is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed -25 to +45 PPM (parts per million) oscillator frequency error at 25oC, which equates to about +1.9 to -1.1 minutes per month (see Figure 20, page 22). When the Calibration circuit is properly employed, accuracy improves to better than +1/-2 PPM at 25C. The oscillation rate of crystals changes with temperature. The M41T81 design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 21, page 22. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration Bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Bits occupy the five lower order bits (D4-D0) in the Control Register 08h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 PPM of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month
which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41T81 may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Application Note AN934, "TIMEKEEPER (R) CALIBRATION." This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT/OUT/SQW pin. The pin will toggle at 512Hz, when the Stop Bit (ST, D7 of 01h) is '0,' the Frequency Test Bit (FT, D6 of 08h) is '1,' the Alarm Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the Square Wave Enable Bit (SQWE, D6 of 0Ah) is '0' and the Watchdog Register (09h = 0) is reset. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 PPM oscillator frequency error, requiring a -10 (XX001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency Test output frequency. The IRQ/FT/OUT/SQW pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500-10k resistor is recommended in order to control the rise time. The FT Bit is cleared on power-down.
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M41T81
Setting Alarm Clock Registers Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every year, month, day, hour, minute, or second. It can also be programmed to go off while the M41T81 is in the battery back-up mode to serve as a system wake-up call. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 11, page 19 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set (and SQWE is '0.'), the alarm condition activates the IRQ/FT/OUT/ SQW pin. Figure 18. Alarm Interrupt Reset Waveform
Note: If the address pointer is allowed to increment to the Flag Register address, an alarm condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a different address. It should also be noted that if the last address written is the "Alarm Seconds," the address pointer will increment to the Flag address, causing this situation to occur. The IRQ/FT/OUT/SQW output is cleared by a READ to the Flags Register as shown in Figure 18. A subsequent READ of the Flags Register is necessary to see that the value of the Alarm Flag has been reset to '0.' The IRQ/FT/OUT/SQW pin can also be activated in the battery back-up mode. The IRQ/FT/OUT/ SQW will go low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set. Figure 19 illustrates the back-up mode alarm timing.
0Eh
0Fh
10h
ACTIVE FLAG
IRQ/FT/OUT/SQW
HIGH-Z
AI04617
Figure 19. Back-up Mode Alarm Waveform
VCC
VSO tREC ABE and AFE Bits AF Bit in Flags Register IRQ/FT/OUT/SQW
HIGH-Z
HIGH-Z
AI05663
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M41T81
Table 11. Alarm Repeat Modes
RPT5 1 1 1 1 1 0 RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm Setting Once per Second Once per Minute Once per Hour Once per Day Once per Month Once per Year
Watchdog Timer The watchdog timer can be used to detect an outof-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the Watchdog Register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3*1, or 3 seconds). If the processor does not reset the timer within the specified period, the M41T81 sets the WDF (Watchdog Flag) and generates a watchdog interrupt.
The watchdog timer can be reset by having the microprocessor perform a WRITE of the Watchdog Register. The time-out period then starts over. Should the watchdog timer time-out, a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ/FT/OUT/SQW pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the Flags Register will reset the Watchdog Flag (Bit D7; Register 0Fh). The watchdog function is automatically disabled upon power-up and the Watchdog Register is cleared. If the watchdog function is set, the frequency test function is activated, and the SQWE Bit is '0,' the watchdog function prevails and the frequency test function is denied.
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M41T81
Square Wave Output The M41T81 offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 12. Once the selection of the Table 12. Square Wave Output Frequency
Square Wave Bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Square Wave Frequency None 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1 Units kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
SQW frequency has been completed, the IRQ/FT/ OUT/SQW pin can be turned on and off under software control with the Square Wave Enable Bit (SQWE) located in Register 0Ah.
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M41T81
Century Bit Bits D7 and D6 of Clock Register 03h contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Output Driver Pin When the FT Bit, AFE Bit, SQWE Bit, and Watchdog Register are not set, the IRQ/FT/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the Control Register. In other words, when D7 (OUT Bit) and D6 (FT Bit) of address loTable 13. Preferred Default Values
Condition Initial Power-up(2) Subsequent Power-up (with battery back-up)(3)
Note: 1. BMB0-BMB4, RB0, RB1. 2. State of other control bits undefined. 3. UC = Unchanged
cation 08h are a '0,' then the IRQ/FT/OUT/SQW pin will be driven low. Note: The IRQ/FT/OUT/SQW pin is an open drain which requires an external pull-up resistor. Preferred Initial Power-on Default Upon initial application of power to the device, the following register bits are set to a '0' state: Watchdog Register; AFE; ABE; SQWE; and FT. The following bits are set to a '1' state: ST; OUT; and HT (see Table 13, page 21).
ST 1 UC
HT 1 1
Out 1 UC
FT 0 0
AFE 0 UC
SQWE 0 UC
ABE 0 UC
WATCHDOG Register(1) 0 0
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M41T81
Figure 20. Crystal Accuracy Across Temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = -0.038 ppm (T - T )2 10% 0 F C2 T0 = 25 C
Temperature C
AI00999
Figure 21. Clock Calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
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M41T81
PACKAGE MECHANICAL INFORMATION Figure 22. SO8 - 8-lead Plastic Small Package Outline
h x 45 A2 B e D A C ddd
8
E
1
H A1 L
SO-A
Note: Drawing is not to scale.
Table 14. SO8 - 8-lead Plastic Small Outline (150 mils body width), Package Mechanical Data
mm Symb Typ A A1 A2 B C D E e H h L N ddd 1.27 Min 1.35 0.10 1.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max 1.75 0.25 1.65 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ Min 0.053 0.004 0.043 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max 0.069 0.010 0.065 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
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M41T81
Figure 23. SOX18 - 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline
D
9 1
h x 45
C E H
10
18
A2 B SO-J
Note: Drawing is not to scale.
A e A1 ddd A1 L
Table 15. SOX18 - 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Mechanical
Symbol A A1 A2 B C D ddd E e H L N 1.27 7.57 - 10.16 0.51 0 18 11.61 millimeters Typ Min 2.44 0.15 2.29 0.41 0.20 11.56 Max 2.69 0.31 2.39 0.51 0.31 11.66 0.10 7.67 - 10.52 0.81 8 0.050 0.298 - 0.400 0.020 0 18 0.457 Typ inches Min 0.096 0.006 0.090 0.016 0.008 0.455 Max 0.106 0.012 0.094 0.020 0.012 0.459 0.004 0.302 - 0.414 0.032 8
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M41T81
Figure 24. SOX28 - 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline
D
14 1
h x 45
C E H
15
28
A2 B SO-E
Note: Drawing is not to scale.
A e A1 ddd A1 L
Table 16. SOX28 - 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Mechanical
Symbol A A1 A2 B C D ddd E e H L N 1.27 7.57 - 10.16 0.51 0 28 millimeters Typ Min 2.44 0.15 2.29 0.41 0.20 17.91 Max 2.69 0.31 2.39 0.51 0.31 18.01 0.10 7.67 - 10.52 0.81 8 0.050 0.298 - 0.400 0.020 0 28 Typ inches Min 0.096 0.006 0.090 0.016 0.008 0.705 Max 0.106 0.012 0.094 0.020 0.012 0.709 0.004 0.302 - 0.414 0.032 8
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M41T81
PART NUMBERING Table 17. Ordering Information Scheme
Example: M41T 81 M 6 TR
Device Type M41T
Supply Voltage and Write Protect Voltage 81 = VCC = 2.0 to 5.5V
Package M = SO8 MX(1) = SOX28 MY(1) = SOX18
Temperature Range 6 = -40C to 85C
Shipping Method for SOIC blank = Tubes TR = Tape & Reel
Note: 1. The SOX28 and SOX18 packages include an embedded 32,768Hz crystal.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M41T81
REVISION HISTORY Table 18. Document Revision History
Date December 2001 21-Jan-02 01-May-02 05-Jun-02 10-Jun-02 03-Jul-02 11-Oct-02 21-Jan-03 05-Mar-03 12-Sep-03 Rev. # 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2.0 First Issue Fix table footnotes (Table 5, 6) Modify reflow time and temperature footnote (Table 2) Modify Data Retention text, Trip Points (Table 9) Corrected Supply Voltage values (Table 2, 3) Modify DC Characteristics, Crystal Electrical table footnotes, Preferred Default Values (Table 5, 6, 13) Add marketing status (Figure 3; Table 17); adjust footnotes (Figure 5; Table 5) Add embedded crystal package option (Figure 2, 7, 24; Table 16); modified preexisting mechanical drawing (Figure 22; Table 14). Correct dimensions (Figure 24; Table 16); remove SNAPHAT(R) package option Updated disclaimer, v2.2 template; add SOX18 package (Figure 3, 6, 23; Table 17, 15) Revision Details
M41T81, 41T81, T81Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect , Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, vIndustrial, Industrial, Industrial, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC
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M41T81
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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